a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device with self-aligned contacts and its manufacture method.
b) Description of the Related Art
In order to achieve high integration and low cost of semiconductor devices, it is necessary to form basic constituents or semiconductor elements as small as possible. In order to make a fine semiconductor element, it is necessary to make a position alignment margin as small as possible which is provided for preventing electrical short or the like between wiring patterns when a contact hole is formed.
A method called self aligned contact (SAC) is known as a method of forming a fine contact hole. This method is disclosed, for example, in JP-A-58-115859.
With this method, after a first insulating film is formed on the gate electrode layer of a MOS transistor, the gate electrode layer is patterned to form a gate electrode. Then, source/drain diffusion regions are formed and thereafter a second insulating film is formed over the whole surface of the substrate. The second insulating film is anisotropically etched to expose the surfaces of the diffusion regions.
With the above processes, the side walls of the gate electrode structure including the first insulating film are covered with the second insulating film. The periphery of the gate electrode can therefore be insulated completely by the first and second insulating films. When a third insulating film having different etching characteristics from the first and second insulating films is formed over the whole surface of the substrate, contact holes can be formed to the diffusion regions in a self-aligned manner.
If a contact window is formed by such a SAC method, a position alignment margin between the underlying conductive layer and a contact hole is not necessary and the cell can be made finer correspondingly.
An example of improved self-aligned contact techniques used for forming a dynamic random access memory (DRAM) cell will be described with reference to the cross sectional views of FIGS. 15A to 15D which illustrate the main manufacture processes thereof.
FIGS. 15A to 15D are cross sectional views showing a typical memory cell portion taken along the direction crossing the word line extending direction. With reference to these Figures, a specific description will be given for a method of forming contact holes to a bit line, a storage electrode and the source/drain diffusion regions of a MOS transistor by using self-aligned contact techniques. First, as shown in FIG. 15A, a gate insulating film 113 is formed on the active region of a silicon substrate 111 defined by a field oxide film 112 made by local oxidation of silicon (LOCOS). On this gate insulating film 113, a polycide gate electrode is formed which is constituted of a polysilicon layer 114 and a tungsten silicide layer 115. By using the gate electrode and LOCOS oxide film as a mask, impurity ions are implanted to form source/drain diffusion regions 116. Next, a nitride film 117 is formed covering the periphery of the polycide gate electrode which corresponds to a word line.
The processes up to this are the same as the above-described self-aligned contact method, and may be performed by the method described in the above-cited JP-A-58-115859.
Next, a silicon oxide film 118 is formed over the whole surface of the substrate. This silicon oxide film is planarized by chemical mechanical polishing (CMP) or the like in order to facilitate later processes.
Next, as shown in FIG. 15B, resist is coated on the planarized oxide film 118 and patterned by usual photolithography to form a resist pattern 119 which is used later as an etching mask.
Next, as shown in FIG. 15C, by using the resist pattern as a mask, the oxide film 118 is etched to form contact holes 120 reaching the diffusion regions 116. The etching conditions are set so as to have a large etching selection ratio of the oxide film relative to the silicon nitride film. Therefore, when the nitride film 117 is exposed while the oxide film is etched, this nitride film is hardly etched. The etching can be stopped automatically at the nitride film 117 so that the contact holes can be formed in a self-aligned manner and have generally the same area as initially defined by the nitride film.
The resist pattern is thereafter removed by known techniques.
Next, as shown in FIG. 15D, a conductive layer 121 is formed in the contact holes.
Even if the contact holes are formed overlapping the upper portion or its nearby portion of the gate electrode structure because of a position misalignment of the resist pattern 119, electrical short will not occur between the conductive layer 121 and the polycide gate electrode. It is not necessary therefore to provide a position alignment margin of the contact holes relative to the polycide electrode.
The above techniques therefore allow to planarize the oxide film 118 as an interlayer insulating film and to form contact holes in a self-aligned manner.
Such a conventional self-aligned contact method is associated, however, with the following problems because of a multi-layer process used for highly integrated semiconductor devices.
There is a great need for reducing the number of processes, for example, by forming wiring layers of the same level at the same time in both a memory cell portion and a peripheral circuit portion or forming contact holes to conductive layers of different levels at the same time in both the portions by the same process.
The problems of conventional techniques will be described more specifically with reference to FIGS. 16A to 16C and FIGS. 17A to 17C.
A first example will be described with reference to FIGS. 16A to 16C.
As shown in FIG. 16A, a gate insulating film 113 is formed on a silicon substrate 111. In the memory cell portion, a polycide gate electrode 115 made of polysilicon and tungsten silicide is formed on the gate insulating film 113. In the peripheral circuit portion, a first wiring layer 115a is formed having the same structure as the polycide gate electrode.
A nitride film 117a is formed on both the polycide gate electrode 115 and first wiring layer 115a. By using at least the polycide gate electrode 115 as a mask, impurities are doped into the silicon substrate 111 to form source/drain diffusion regions (not shown).
Next, as shown in FIG. 16B, spacers made of nitride are formed on the side walls of the polycide gate electrode 115 and first wiring layer 115a to thereby form a nitride film 117 which covers the outer surfaces of the polycide gate electrode 115 and first wiring layer 115a. This polycide gate electrode corresponds to a word line.
Next, a silicon oxide film 118 is formed over the whole surface of the substrate. This silicon oxide film is planarized by CMP or the like in order to facilitate later processes.
Next, as shown in FIG. 16C, resist is coated on the planarized oxide film 118 and patterned by usual photolithography to form a resist pattern 119.
By using the resist pattern 119 as a mask, the silicon oxide film 118 is etched to form a contact hole 120a reaching the source/drain diffusion region (not shown) and a contact hole 120b reaching the nitride film 117 on the first wiring layer 115a. The etching conditions are set so as to have a large etching selection ratio of the silicon oxide film to the silicon nitride film.
The processes up to this are conventional techniques using self-aligned contact. Since the nitride film 117 on the first wiring layer 115a is hardly etched, it is not possible to form both the contact holes to the source/drain diffusion region and first wiring layer by a single process.
In order to electrically connect the same wiring layer to both the source/drain diffusion region and first wiring layer in contact holes, the nitride film 117 on the first wiring layer 115a is required to be etched. Therefore, it is necessary to perform photolithography once more, lowering the manufacture yield.
A second example will be described with reference to FIGS. 17A to 17C.
As shown in FIG. 17A, a gate insulating film 113 is formed on a silicon substrate 111. In the memory cell portion, a polycide gate electrode 115 made of polysilicon and tungsten silicide is formed on the gate insulating film 113. In the peripheral circuit portion, a first wiring layer 115a is formed having the same structure as the polycide gate electrode. By using at least the polycide gate electrode 115 as a mask, impurities are doped into the silicon substrate 111 to form source/drain diffusion regions (not shown). Both the polycide gate electrode 115 and first wiring layer 115a are covered with an oxide film 127. The polycide gate electrode corresponds to a word line.
Next, as shown in FIG. 17B, a silicon oxide film 137 and a nitride film 147 are sequentially formed. Then, another silicon oxide film 118 is formed over the whole surface of the substrate. This silicon oxide film 118 is planarized by CMP or the like in order to facilitate later processes.
Next, as shown in FIG. 17C, by using a resist pattern (not shown) as a mask, the silicon oxide film 118 is etched to form a contact hole 120a reaching the source/drain diffusion region (not shown) and a contact hole 120b reaching the silicon oxide film 127 on the first wiring layer 115a.
In this case, in etching the contact holes, the silicon oxide film 118 is etched at the first stage at a large etching ratio of the silicon oxide film to the nitride film. At the second stage the nitride film 147 is etched at a large etching ratio of the nitride film to the silicon oxide film. At the third stage, the silicon oxide film 137 is etched. With this method, the contact hole 120a can be formed in a self-aligned manner relative to the polycide gate electrode 115.
The processes up to this are conventional techniques using self-aligned contact. Also in this second example, the problem same as described in the first example occurs.
Specifically, since the oxide film 127 on the first wiring layer 115a is hardly etched, it is not possible to form both the contact holes to the source/drain diffusion region and first wiring layer by a single process.
The two self-aligned contact methods of the first and second examples are characterized in the formation of a nitride film on the polycide gate electrode. By using this nitride film as a stopper of etching the silicon oxide film, contact holes are formed in a self-aligned manner.
In order to electrically connect the same wiring layer to both the source/drain diffusion region and first wiring layer through contact holes, by using the above-described contact hole etching methods, it is necessary to form a contact hole to the first wiring layer through another photolithography different from that used for forming a contact hole to the source/drain diffusion regions. This increases the number of processes.
Low cost of semiconductor device manufacture processes is an important technical issue. If a single patterning process in particular can be omitted, a series of resist coating, exposure and development processes can be all omitted. Therefore, this patterning process is very important.